`timescale 1ns/1ps
// -----------------------------------------------------------------------------
// Copyright (c) 2014-2023 All rights reserved
// *********************************************************************************
// Project Name : 
// Author       : Dark
// Create Time  : 2023-01-31 10:49:31
// Revise Time	: 2023-01-31 10:49:31
// File Name    : imm_gen.sv
// Abstract     :
`include "defines.svh"

module imm_gen (
	input	logic 	[31:0]	instr,

	output	logic	[31:0]	imm
);

//=================================================================================
// Signal declaration
//=================================================================================
	logic	[31:0]	immI;
	logic	[31:0]	immU;
	logic	[31:0]	immS;
	logic	[31:0]	immB;
	logic	[31:0]	immJ;
	logic	[ 6:0]	op  ;

//=================================================================================
// Body
//=================================================================================
	assign op   = instr[6:0];
	assign immI = {{20{instr[31]}}, instr[31:20]};
	assign immU = {instr[31:12], 12'b0};
	assign immS = {{20{instr[31]}}, instr[31:25], instr[11:7]};
	assign immB = {{20{instr[31]}}, instr[7], instr[30:25], instr[11:8], 1'b0};
	assign immJ = {{12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1'b0};

	always_comb begin
		case (op)
			`OP_LUI,`OP_AUIPC		:	imm = immU;
			`OP_I,`OP_JALR,`OP_LD 	:   imm = immI;
			`OP_JAL 				: 	imm = immJ;
			`OP_B 					:	imm = immB;							// B-type ==> if
			`OP_S 					:	imm = immS;	
			default 				:	imm = 32'b0;
		endcase
	end	
endmodule 
